“..., respectively. Moreover, the compact de-glitch latch simplifies the conventional latch design and layout...”
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“...-speed analog-to-digital converters (ADCs). The first design is a 5-bit 1-Gsample/s flash ADC fabricated...”
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“...碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === 　In this thesis, a 10-bit 1-GSample/s segmented digital...”
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“... converter using TSMC 0.13-�慆 1P8M CMOS process is designed in this thesis. Post-layout simulation results...”
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“.... The chip occupies 3.57 mm2 die area and the digital part occupies half of the area. The post-layout...”
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