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1“... for the premise part of a dual-input single-output fuzzy logic controller. The control circuit is designed...”
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2“...; therefore, we can logic synthesis and then complete digital IF down converter design. ...”
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3“... by digital logic chips and a control circuit driven by a brushless DC motor was manufactured to substitute...”
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4“... become a standard hardware description language, Popularly use in VLSI and Digital System Design...”
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5“.... Then the simplified code is fed into Synopsys Design Compiler for further logic minimization and technology mapping...”
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6“... direct Torque Control (DTC) for Induction Motors. Describe with Verilog HDL that writes every mould group...”
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7by 顏文偉“... signals and the energy signals are fed to the time-to-digital converter (TDC) units and Amplitude-to-Time...”
Published 2014
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8“... designed in a full-custom design manner. However, this work is completely implemented with the logic gates...”
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9by 楊溢棋“... HDL (Hardware Description Language) and Altera FPGA (Field Programmable Gate Array) to design...”
Published 2002
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10“...: Arithmetic and Logic Unit;ALU Register Control Unit;CU Memory Use hierarchical design concept and when every...”
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11“... based on Microchip PIC16LF84 specifications from the mid-range PIC series, and completes the digital...”
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12“..., and finally applying Design Compiler Tools to perform logic synthesis using TSMC 0.18μm 1P6M Process Cell...”
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13“... Verilog HDL (Hardware Design Language) simulation with ModelSim, and compiled with FPGA Compile II...”
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14“... by the National Chip Implementation Center (CIC), thereby completing the digital integrated circuit design process...”
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15“... digital CMOS chip. In the near future, ASICs will use up to 15 million logic gates, and only a small...”
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16“...-radix and signed digit number techniques are thus proposed. However, the quotient selection logic...”
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17“... is designed for real-time digital video data and the processing data rate is more than 50 MHz...”
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18“..., we used hardware describe languages (HDL) and a complex programmable logic device (CPLD) to develop...”
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19“... chips are integrated on a single FPGA chip. In digital logic chips, HDL (Hardware Description Language...”
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20“...-bits.After the HDL simulations and logic synthesis by TSMC 0.18μm process in DR 32-bits, the chip area...”
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