Showing 1 - 17 results of 17 for search 'DIGITAL SIGNAL PROCESSING', query time: 0.94s Refine Results
  1. 1
    Design of a Digital Pulse-Width Locked Loop
    by Zeng-Jia Lu, 呂政家
    Published 2008
    “... the signal integrity, especially when the circuit is complicated and operated in high clock frequency...”
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  2. 2
    Design of High-Speed Pipelined Analog-to-Digital Converters
    by Shin-SyongHuang, 黃詩雄
    Published 2010
    “..., and they are widely adopted in wireless communication, video and digital-signal-processing (DSP) systems. Thanks...”
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  3. 3
    An Automated Synthesis Tool for Pipelined Analog-to-Digital Converters
    by Ya-Ting Shyu, 許雅婷
    Published 2008
    “... for mixed-signal circuits to speedup the design process is more and more important. Analog-to-digital...”
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  4. 4
    An Analog-to-Digital Converter with Dual Nyquist and Oversampling Modes
    by Gia-HuangChen, 陳家煌
    Published 2012
    “.... Nyquist-rate mode and oversampling mode, analog-to-digital converter (ADC) for multiple specifications...”
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  5. 5
    Design and Test of Low Power Pipelined/Cyclic Analog-to-Digital Converters
    by Jin-FuLin, 林進富
    Published 2010
    “... is implemented in a pure digital 0.18?um 1P5M CMOS process. The double loading problem of conventional CDS...”
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  6. 6
    Testing and Built-In Self-Test Techniques for Analog and Mixed-Signal Circuits
    by Soon-Jyh Chang, 張順志
    Published 2002
    “... and built-in self-test for analog and mixed-signal circuits. First, it proposes a systematic method...”
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  7. 7
    The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters
    by Su-Ling Huang, 黃素鈴
    Published 2008
    “..., and practical considerations of implementation for a 10-bit 500-MSample/s current steering digital-to-analog...”
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  8. 8
    Design Automation and Error Analysis for Successive Approximation Register Analog-to-Digital Converters
    by Chun-PoHuang, 黃俊博
    Published 2016
    “...博士 === 國立成功大學 === 電機工程學系 === 104 === Successive approximation register (SAR) analog-to-digital...”
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  9. 9
    An 11-Bit 20-MS/s Wide Input Range Successive-Approximation Analog-to-Digital Converter
    by Wen-ChiaLuo, 羅文佳
    Published 2019
    “...-approximation register (SAR) analog-to-digital converter (ADC), which can be easily integrated into high-voltage...”
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  10. 10
    Design of a Simple Pulse Width Control Loop Circuit by Using Digital Frequency Dividers
    by Chi-Ching Chen, 陳基清
    Published 2007
    “...碩士 === 國立成功大學 === 電機工程學系碩博士班 === 95 === Most digital and mixed-signal circuits use a lot of clock...”
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  11. 11
    A High-Speed Pipelined Analog-to-Digital Converter Using Wide-band Sample-and-Hold Amplifier
    by Tz-Jing Shau, 邵姿菁
    Published 2009
    “.... However, the signal dynamic range will be decreased because of the reduction of supply voltage. In order...”
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  12. 12
    A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC with Digital Code Error Correction
    by Chia-HsinLee, 李佳欣
    Published 2016
    “...-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison...”
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  13. 13
    Detection System for Capacitive Plantar Pressure Monitoring
    by Tzung-Min Tsai, Shuenn-Yuh Lee, Soon-Jyh Chang
    Published 2020-01-01
    Subjects: “...analog-to-digital converter...”
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  14. 14
    Design and Implementation of a Multi-resolution Built-In Self-Test Circuit for Jitter Measurement
    by Shih-Ming Luo, 羅世明
    Published 2007
    “... oscillator based time-to-digital converter (TDC). A pulse amplifier is used to linearly amplify the time...”
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  15. 15
    Design of Stable Reference Voltage Generator and Temperature Sensing System for System Chip Applications
    by Peng-YuChen, 陳鵬宇
    Published 2014
    “...博士 === 國立成功大學 === 電機工程學系 === 102 === Analog and mixed-signal circuits are sensitive to many factors...”
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  16. 16
    A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure
    by Ting-ZiChen, 陳亭諮
    Published 2012
    “... to arrange a new switching scheme. This analog to digital converter possesses a predictive circuit in order...”
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  17. 17
    Design for Clock and Data Recovery Circuits and Quick Estimation for Jitter Tolerance
    by Yen-LongLee, 李彥龍
    Published 2017
    “...) circuits are widely used. In a noisy transmission environment which causes poor signal integrity, the CDR...”
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