Showing 1 - 20 results of 22 for search 'IC DESIGN AND FABRICATION', query time: 0.72s Refine Results
  1. 1
    System-Level ESD Protection Design in CMOS ICs With Transient Detection Circuits
    by Yen, Cheng-Cheng, 顏承正
    Published 2009
    “... primary reliability issue in CMOS integrated circuit (IC) products. With more and more complicated design...”
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  2. 2
    On-Chip ESD Protection Design for High-Voltage ICs in 100 ~ 200V SOI Process
    by Huang, Yi-Jie, 黃義傑
    Published 2015
    “... and many integrated circuits (ICs) of electrical products fabricated in a high-voltage (HV) process...”
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  3. 3
    Advanced ESD Protection Design for Nanoscale CMOS Processes
    “... serious issue. When transistors are fabricated with gate oxide of only a few nanometers thick, the gate...”
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  4. 4
    ESD Protection Design for Radio-Frequency Integrated Circuits
    by Tsai, Shiang-Yu, 蔡翔宇
    Published 2012
    “...-frequency integrated circuits (RF ICs) have been fabricated in CMOS processes. Electrostatic discharge (ESD...”
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  5. 5
    Design and Applications of ESD Protection in High-Voltage Integrated Circuits
    by Chen, Wen-Yi, 陳穩義
    Published 2011
    “... protection design in chapter 6 is for ICs with a voltage programming (VPP) pin. When programming read only...”
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  6. 6
    DESIGN AND IMPLEMENTATION TO IMPROVE LATCHUP IMMUNITY OF CMOS INTEGRATED CIRCUITS
    by Tsai, Hui-Wen, 蔡惠雯
    Published 2015
    “... are applied in the high-voltage (HV) environment (as for the Power IC design like the AC-DC and DC-DC...”
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  7. 7
    Design of 8-bit Thermal-to-Digital Converter in CMOS Technology
    by Chien, Ming-Cheng, 簡銘成
    Published 2001
    “.... Usually, there is an offset problem in CMOS analog or mixed-signal IC design. In this thesis, a method...”
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  8. 8
    ESD Protection Design and Latchup Prevention in High-Voltage BCD Technology
    by Dai, Chia-Tsen, 戴嘉岑
    Published 2017
    “.... ESD protection design is therefore necessary to protect ICs from being damaged by ESD stress energies...”
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  9. 9
    Study of Electrostatistic Discharge Protection Design in High-Voltage BCD Processes
    by Dai, Chia-Tsen, 戴嘉岑
    Published 2012
    “.... ESD protection design is therefore necessary to protect ICs from being damaged by ESD stress energies...”
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  10. 10
    Reliability Design of ESD Clamp Circuit and Output Buffer for SoC Applications
    by Chiu, Po-Yen, 邱柏硯
    Published 2013
    “.... With the development of SoC applications, the high-voltage CMOS technology is widely adapt in the ICs fabrication...”
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  11. 11
    High-Reliability and Low-Capacitance Bond Pad Design for CMOS Integrated Circuits
    by Peng, Jeng-Jie, 彭政傑
    Published 2002
    “... correlated approaches of bond pad designs of wire bond IC products proposed for reliability improvement...”
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  12. 12
    ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology
    by Fan, Mei-Lian, 范美蓮
    Published 2014
    “..., radio-frequency integrated circuits (RF ICs) have been fabricated in nanoscale CMOS processes...”
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  13. 13
    Design Optimization and Failure Analysis of On-Chip ESD Protection in CMOS Integrated Circuits
    by Chen, Shih-Hung, 陳世宏
    Published 2009
    “... into consideration during the design phase of all IC products. In order to prevent the ESD failures and damages in IC...”
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  14. 14
    DESIGN AND IMPLEMENTATION OF ESD PROTECTION CIRCUITS IN NANOSCALE FULLY SILICIDED CMOS TECHNOLOGY
    by Yeh, Chih-Ting, 葉致廷
    Published 2013
    “..., the fabricated cost per unit area of the IC is dramatically increased with the continuously scaled-down CMOS...”
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  15. 15
    Low-Leakage Power-Rail ESD Protection Designs in CMOS Integrated Circuits
    by Wang, Chang-Tzu, 王暢資
    Published 2010
    “... for high-voltage IC products. In this dissertation, the ESD design constraints in nanoscale CMOS process...”
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  16. 16
    ESD Protection Design in 28nm High-K / Metal Gate Process
    by Chang, Pin-Hsin, 張品歆
    Published 2014
    “..., the devices in the integrated circuits (ICs) have been fabricated with ultra-thin gate oxide thickness...”
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  17. 17
    Protection Design against Charged-Device-Model ESD Events in CMOS Integrated Circuits
    by Chang, Tang-Long, 張堂龍
    Published 2010
    “... in the integrated circuits (ICs) have been fabricated with very thin gate oxide to achieve high-speed and low- power...”
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  18. 18
    SCR-Based ESD Protection Designs for Radio-Frequency Integrated Circuits in Fully Silicided CMOS Process
    by Lin, Chun-Yu, 林群祐
    Published 2009
    “... be taken into consideration during the design phase of all IC products. All pads which connect the IC...”
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  19. 19
    ESD Protection Design of 900–1800MHz High-Power CMOS T/R Switch for GSM Cellular Applications
    by Hung, Tao-Yi, 洪道一
    Published 2017
    “... current. The proposed ESD protection design for high-power T/R switch has been fabricated in a 0.18-µm...”
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  20. 20
    Optimization of Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Layout Consideration
    by Liao, Seian-Feng, 廖顯峰
    Published 2015
    “... (HV) applications. ESD may occur accidentally during the fabrication, package, and assembling...”
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