Showing 1 - 20 results of 184 for search 'LEVEL DESIGN', query time: 1.10s Refine Results
  1. 1
    Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs
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  2. 2
    An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs
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  3. 3
    Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver
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  4. 4
    Ultrasonic imaging front-end design for CMUT: A 3-level 30Vpp pulse-shaping pulser with improved efficiency and a noise-optimized receiver
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  5. 5
    Constructing Symbolic Representations for High-Level Planning
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  6. 6
    On the flow-level dynamics of a packet-switched network
    by Moallemi, Ciamac C., Shah, Devavrat
    Published 2012
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  7. 7
    Deconvolution of Serum Cortisol Levels by Using Compressed Sensing
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  8. 8
    A general technique for deterministic model-cycle-level debugging
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  9. 9
    Darsim: A Parallel Cycle-Level NoC Simulator
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  10. 10
    Tight Revenue Bounds With Possibilistic Beliefs and Level-k Rationality
    by Chen, Jing, Micali, Silvio, Pass, Rafael
    Published 2016
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    Article
  11. 11
    Separation of concerns for dependable software design
    by Jackson, Daniel, Kang, Eunsuk
    Published 2011
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  12. 12
    Enabling System-Level Modeling of Variation-Induced Faults in Networks-on-Chip
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  13. 13
    An electrical-level superposed-edge approach to statistical serial link simulation
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  14. 14
    Reading Between the Lines: Learning to Map High-level Instructions to Commands
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  15. 15
    A design flow based on modular refinement
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  16. 16
    Photonics design tool for advanced CMOS nodes
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  17. 17
    Non-convex optimization for the design of sparse FIR filters
    by Wei, Dennis
    Published 2010
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  18. 18
    Foundry: Hierarchical Material Design for Multi-Material Fabrication
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  19. 19
    Efficient baseband design and implementation for high-throughput transmitters
    “... AMO SCS design achieves 2× area reduction over the register-based design at the same throughput...”
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  20. 20
    Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos
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