Showing 1 - 20 results of 21 for search 'MECHANICAL AND DIGITAL DESIGN', query time: 0.60s Refine Results
  1. 1
    A reliability analysis approach to assist the design of aggressively scaled reconfigurable architectures
    by Pereira, Mônica Magalhães
    Published 2012
    “.... In this context, this work present a comprehensive analysis of architectural design that includes the use...”
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    Others
  2. 2
    A reliability analysis approach to assist the design of aggressively scaled reconfigurable architectures
    by Pereira, Mônica Magalhães
    Published 2012
    “.... In this context, this work present a comprehensive analysis of architectural design that includes the use...”
    Get full text
    Others
  3. 3
    A reliability analysis approach to assist the design of aggressively scaled reconfigurable architectures
    by Pereira, Mônica Magalhães
    Published 2012
    “.... In this context, this work present a comprehensive analysis of architectural design that includes the use...”
    Get full text
    Others
  4. 4
    Redes-em-chip para sistemas embarcados visando a otimização de medidas de qualidade de serviço para aplicações de tempo real
    by Corrêa, Edgard de Faria
    Published 2008
    “..., but their designs are more complex. One of the problems to solve is the design of the communication infrastructure...”
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    Others
  5. 5
    Redes-em-chip para sistemas embarcados visando a otimização de medidas de qualidade de serviço para aplicações de tempo real
    by Corrêa, Edgard de Faria
    Published 2008
    “..., but their designs are more complex. One of the problems to solve is the design of the communication infrastructure...”
    Get full text
    Others
  6. 6
    Redes-em-chip para sistemas embarcados visando a otimização de medidas de qualidade de serviço para aplicações de tempo real
    by Corrêa, Edgard de Faria
    Published 2008
    “..., but their designs are more complex. One of the problems to solve is the design of the communication infrastructure...”
    Get full text
    Others
  7. 7
    Gerenciamento automático de recursos reconfiguráveis visando a redução de área e do consumo de potência em dispositivos embarcados
    by Rutzig, Mateus Beck
    Published 2008
    “... device has driven designers to create novel solutions to increase the performance of embedded processors...”
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    Others
  8. 8
    Gerenciamento automático de recursos reconfiguráveis visando a redução de área e do consumo de potência em dispositivos embarcados
    by Rutzig, Mateus Beck
    Published 2008
    “... device has driven designers to create novel solutions to increase the performance of embedded processors...”
    Get full text
    Others
  9. 9
    Gerenciamento automático de recursos reconfiguráveis visando a redução de área e do consumo de potência em dispositivos embarcados
    by Rutzig, Mateus Beck
    Published 2008
    “... device has driven designers to create novel solutions to increase the performance of embedded processors...”
    Get full text
    Others
  10. 10
    Virtualização de hardware e exploração da memória de contexto em arquiteturas reconfiguráveis
    by Ló, Thiago Berticelli
    Published 2013
    “... the design space with the objective of reducing both area and energy consumption, and presents two hardware...”
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    Others
  11. 11
    Virtualização de hardware e exploração da memória de contexto em arquiteturas reconfiguráveis
    by Ló, Thiago Berticelli
    Published 2013
    “... the design space with the objective of reducing both area and energy consumption, and presents two hardware...”
    Get full text
    Others
  12. 12
    Virtualização de hardware e exploração da memória de contexto em arquiteturas reconfiguráveis
    by Ló, Thiago Berticelli
    Published 2013
    “... the design space with the objective of reducing both area and energy consumption, and presents two hardware...”
    Get full text
    Others
  13. 13
    Fine-grained error detection techniques for fast repair of FPGAs
    by Nazar, Gabriel Luca
    Published 2013
    “... throughput, flexibility and reduced design time are among the main assets of such devices, and are essential...”
    Get full text
    Others
  14. 14
    Fine-grained error detection techniques for fast repair of FPGAs
    by Nazar, Gabriel Luca
    Published 2013
    “... throughput, flexibility and reduced design time are among the main assets of such devices, and are essential...”
    Get full text
    Others
  15. 15
    Fine-grained error detection techniques for fast repair of FPGAs
    by Nazar, Gabriel Luca
    Published 2013
    “... throughput, flexibility and reduced design time are among the main assets of such devices, and are essential...”
    Get full text
    Others
  16. 16
    A generic processing in memory cycle accurate simulator under hybrid memory cube architecture
    “... have designed our mechanism using the SystemC programming language, which allows native parallel...”
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    Others
  17. 17
    A generic processing in memory cycle accurate simulator under hybrid memory cube architecture
    “... have designed our mechanism using the SystemC programming language, which allows native parallel...”
    Get full text
    Others
  18. 18
    A generic processing in memory cycle accurate simulator under hybrid memory cube architecture
    “... have designed our mechanism using the SystemC programming language, which allows native parallel...”
    Get full text
    Others
  19. 19
    Sistema de tradução binária de dois níveis para execução multi-ISA
    by Fajardo Junior, Jair
    Published 2012
    “... possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues, since...”
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    Others
  20. 20
    Sistema de tradução binária de dois níveis para execução multi-ISA
    by Fajardo Junior, Jair
    Published 2012
    “... possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues, since...”
    Get full text
    Others
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