Showing 1 - 13 results of 13 for search 'VLSI SYSTEM DESIGN', query time: 0.61s Refine Results
  1. 1
    VLSI Implementation of Real-Time Two-Dimensional Discrete Cosine Transform
    by Lu, Miin Nan, 盧敏男
    Published 1996
    “... processing technology for dig-ital data compression systems . The goal...”
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  2. 2
    GHz PLL with Built-In Jitter Test Design
    by Shu-Yu Jiang, 江書育
    Published 2003
    “... of the semiconductor process, the operating frequency of VLSI circuits has improved rapidly [1]. Specifically...”
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  3. 3
    Low-Power and Low Phase-Error Phase-Locked Loop Design
    by Lin-Jiunn Tzou, 鄒林俊
    Published 2000
    “... of the mobile electronic systems , low power consumption has become the main concern in the modern VLSI design...”
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  4. 4
    Design of Delay-Locked Loop with Fast-Lock and Wide-Range Operation
    by Yu-Lung Lo, 羅有龍
    Published 2003
    “...碩士 === 淡江大學 === 電機工程學系 === 91 === As the speed performance of VLSI systems increases rapidly, more...”
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  5. 5
    Design and Application of New Double Edge Triggered D-type Flip-Flop
    by Yung-Hsiang Lin, 林永祥
    Published 2003
    “...碩士 === 淡江大學 === 電機工程學系 === 91 === In the modern VLSI design, the System-on-a-Chip (SoC) is becoming...”
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  6. 6
    Design of Low-Jitter Adaptive Bandwidth PLL Based on Self-Biased Techniques
    by Ching-Wen Lai, 賴敬文
    Published 2005
    “... (System-On-a-Chip Design ) is developed, however, there is often phase error or clock skew which generates...”
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  7. 7
    Design and Implementation of 1-Volt GHz and Fast-Locking Phase-Locked Loop
    by Shu-Chang Kuo, 郭書菖
    Published 2004
    “...碩士 === 淡江大學 === 電機工程學系 === 92 === Abstract: The VLSI techniques have developed...”
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  8. 8
    A 2.5GHz Fast Locking Self-Calibration Phase-Locked Loop Designed in 90nm Process
    by Yu-Fen Lin, 林鈺芬
    Published 2008
    “...碩士 === 國立中央大學 === 電機工程研究所 === 96 === The performance and speed of VLSI circuits grew up with scale...”
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  9. 9
    Built-In Jitter Measurement Circuit for 2.5GHz Phase-Locked Loop
    by Pei-yi Jian, 簡佩怡
    Published 2007
    “...(SOC) is the current trend of VLSI circuit. When many systems were integrated into a chip...”
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  10. 10
    An Improved Pulse Shrinking Delay Element for Clock Jitter Measurement
    by Fang-Ying Su, 蘇芳瑩
    Published 2008
    “... trend of VLSI circuit is System-on-Chip (SOC). When many systems were integrated into a chip, the system...”
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  11. 11
    All Digital CMOS Self-sample Vernier Delay Line Circuit for Clock Jitter Measurement
    by Chan-Wei Huang, 黃展緯
    Published 2006
    “...碩士 === 國立中央大學 === 電機工程研究所 === 94 === As the improvement of semiconductor technology, VLSI circuits...”
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  12. 12
    A novel All Digital Phase Locked Loop (ADPLL) with ultra fast frequency lock and high oscillation frequency
    by Chen Yu-Jung, 陳育融
    Published 2001
    “... in many digital or communication systems . In the traditional Phase Locked Loop scheme , the low-pass...”
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  13. 13
    A high precision fast locking arbitrary duty cycle clock synchronization circuit
    by Chi-Hsiang Chen, 陳濟祥
    Published 2008
    “...碩士 === 國立中央大學 === 電機工程研究所 === 97 === Clock synchronization plays a important role in designing VLSI...”
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