Showing 1 - 20 results of 30 for search '王行健', query time: 0.18s Refine Results
  1. 1
    Enhanced Chip Probing Productivity by Six Sigma DMAIC Methodology
    by 王行健
    Published 2008
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  2. 2
    The Design of Entrance Area and Native Taiwan Plant Garden in National Botanical Gardens
    by Wang,Shyng Jian, 王行健
    Published 1993
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  3. 3
    A Study on Hardware Trojans Construction and Detection Based on Layout Information
    by Kuo-Yang Hsu, 許國揚
    Published 2018
    Other Authors: “...王行健...”
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  4. 4
    Low-Power Delay Test Architecture for Pre-Bond Test
    by Han-Hsian Hsu, 許漢軒
    Published 2011
    Other Authors: “...王行健...”
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  5. 5
    High Level Synthesis Methodology for Highly Testable and Nonzero Clock Skew Low Power Design
    by Tung-Hua Yeh, 葉東樺
    Published 2011
    Other Authors: “...王行健...”
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  6. 6
    Clock Tree Optimization with Prebond Testability in 3D IC
    by Yu-Chang Hung, 洪毓章
    Published 2011
    Other Authors: “...王行健...”
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  7. 7
    A Novel Delay Test Method Considering Layout and Power Consumption Information
    by Chia-Han Chung, 鍾佳翰
    Published 2011
    Other Authors: “...王行健...”
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  8. 8
    Dynamic test compaction targeted for test architecture with output compaction
    by Wei-Cheng Lin, 林瑋承
    Published 2012
    Other Authors: “...王行健...”
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  9. 9
    Rewiring for low power
    by 李廣為
    Published 2003
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  10. 10
    Reducing Test Power in Linear Test Data Compression Schemes
    by Yu-De Liao, 廖育德
    Published 2010
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  11. 11
    Low Power Multiplier with Column Bypassing
    by 温明振
    Published 2004
    Other Authors: “...王行健...”
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  12. 12
    Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage
    by Kuo-Lin Peng, 彭國霖
    Published 2006
    Other Authors: “...王行健...”
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  13. 13
    Low Peak Power Test Generation for Broad-side Transition Patterns Based on Don’t-Care Filling
    by Yan-Ting Chen, 陳彥廷
    Published 2006
    Other Authors: “...王行健...”
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  14. 14
    Transition Fault ATPG Based on Stuck-At Fault Test Patterns
    by Yan-Nan Lin, 林彥男
    Published 2006
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  15. 15
    Design and Analysis of Low Cost Output Compressor
    by Yun-Lung Chu, 朱韻龍
    Published 2009
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  16. 16
    Reducing Test Cost of Sequential Machines with Lower Hardware Overhead
    by 王啟信
    Published 1994
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  17. 17
    Structural precomputation design for low-power logic synthesis
    by 王瑛嘉
    Published 2002
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  18. 18
    Lower Hardware Redundancy TSC For Finite State Machine Output Using Berger Code
    by 陳勁興
    Published 2002
    Other Authors: “...王行健...”
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  19. 19
    A Study on the Selection of LFSR's Characteristic Polynomial
    by Waiting Liu, 劉威廷
    Published 2002
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  20. 20
    A concurrent error detedtion method.based on addition and subtraction operations
    by 黃建峰
    Published 2002
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