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Aryadeep Chirag
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Aryadeep Chirag
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Aryadeep Chirag
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1
120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process
by
Deivasigamani Ravi
,
Sheu Gene
,
Aryadeep
Chirag
,
Sai S. Krishna
,
Selvendran S.
,
Yang Shao-Ming
Published 2018-01-01
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Article
2
Gate Engineering in SOI LDMOS for Device Reliability
by
Aanand
,
Sheu Gene
,
Imam Syed Sarwar
,
Lu Shao Wei
,
Aryadeep
Chirag
,
Yang Shao Ming
Published 2016-01-01
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