A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing

by Mário P. Véstias
Published 2019-07-01

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

by Mário P. Véstias, Horácio C. Neto
Published 2021-06-01

Hyperspectral Compressive Sensing With a System-On-Chip FPGA

by Jose M. P. Nascimento, Mario P. Vestias, Gabriel Martin
Published 2020-01-01

Moving Deep Learning to the Edge

by Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Published 2020-05-01

Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning

by Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
Published 2019-11-01

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs

by Mario P. Vestias, Rui P. Duarte, Jose T. De Sousa, Horacio C. Neto
Published 2020-01-01

IOb-Cache: A High-Performance Configurable Open-Source Cache

by João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa
Published 2021-07-01

Coarse-Grained Reconfigurable Computing with the Versat Architecture

by João D. Lopes, Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, José T. de Sousa 
Published 2021-03-01

A Full Featured Configurable Accelerator for Object Detection With YOLO

by Daniel Pestana, Pedro R. Miranda, Joao D. Lopes, Rui P. Duarte, Mario P. Vestias, Horacio C. Neto, Jose T. De Sousa
Published 2021-01-01