Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

by Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
Published 2009-01-01

Efficient Realization of BCD Multipliers Using FPGAs

by Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini
Published 2017-01-01

Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization

by Mountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane
Published 2021-08-01