A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time Delta Sigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 mu m CMOS

by Park, Matthew, Perrott, Michael H.
Published 2010

A single-slope 80MS/s ADC using two-step time-to-digital conversion

by Park, Min, Perrott, Michael H.
Published 2010

A VCO-based analog-to-digital converter with second-order sigma-delta noise shaping

by Park, Min, Perrott, Michael H.
Published 2010

A low jitter programmable clock multiplier based on a pulse injection-locked oscillator with a highly-digital tuning loop

by Perrott, Michael H., Johnson, Kerwin, Hsu, Chun-Ming, Helal, Belal M.
Published 2010

High speed analog-to-digital conversion with silicon photonics

by Schulein, Robert T., Grein, Matthew E., Yoon, Jung Uk, Lennon, Donna M., Geis, Michael W., Lyszczarz, Theodore M., Spector, Steven Jay, Zhou, G. R., Smith, Henry Ignatius, Ram, Rajeev J., Popovic, Milos, Perrott, Michael H., Park, M., Orcutt, Jason Scott, Motamedi, Ali R., Kim, M., Kim, J., Khilo, Anatol M., Kaertner, Franz X., Ippen, Erich P., Hoyt, Judy L., Gan, Fuwan, DiLello, Nicole Ann, Dahlem, Marcus Vinicius Sobral, Chen, J., Byun, Hyunil, Birge, Jonathan R., Araghchini, Mohammad, Amatya, Reja, Holzwarth, Charles W., Shmulovich, J., Hanjani, A., Frolov, S.
Published 2010

A 0.13[mu]m CMOS 78dB SNDR 87mW 20MHz BW CT [Delta Sigma] ADC with VCO-based integrator and quantizer

by Park, Matthew
Published 2010