Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology

by Pedro André Martins Bezerra, Florian Krismer, Johann Walter Kolar, Riduan Khaddam-Aljameh, Stephan Paredes, Ralph Heller, Thomas Brunschwiler, Pier Andrea Francese, Thomas Morf, Marcel André Kossel, Matthias Braendli
Published 2021-05-01