Showing 1 - 20 results of 69 for search 'Shih-Hsu Huang', query time: 0.13s Refine Results
  1. 1
    A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process
    by Che-Wei Tung, Shih-Hsu Huang
    Published 2020-01-01
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    Article
  2. 2
    Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing
    by Hsu-Yu Kao, Xin-Jia Chen, Shih-Hsu Huang
    Published 2021-07-01
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    Article
  3. 3
    Power Optimization for Activity-Driven Clock Trees
    by Chen-Hsien Lin, 林誠憲
    Published 2018
    Other Authors: “...Shih-Hsu Huang...”
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  4. 4
    A New Dynamic Clock Skew Control Mechanism and Its Corresponding Adjustable Delay Buffer Design
    by Chia-Wen Chang, 張嘉文
    Published 2018
    Other Authors: “...Shih-Hsu Huang...”
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  5. 5
    Two-Stage Multi-bit Flip-Flop Clustering for Low Power
    by Chu-Han Hsu, 許筑涵
    Published 2018
    Other Authors: “...Shih-Hsu Huang...”
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  6. 6
    A Design Partitioning Approach for Three Dimensional Integrated Circuits
    by Hua-Hsin Yeh, 葉驊昕
    Published 2010
    Other Authors: “...Shih-Hsu Huang...”
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  7. 7
    Low-Power Clock Tree Synthesis Based on the Characteristics of Cell Library
    by Shao-En Chen, 陳劭恩
    Published 2013
    Other Authors: “...Shih-Hsu Huang...”
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  8. 8
    The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs
    by Yao-Chung Cheng, 鄭曜鐘
    Published 2013
    Other Authors: “...Shih-Hsu Huang...”
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  9. 9
    Using Cell Characteristics to Minimize the Aging Effect on Clock Skew
    by Ming-Chieh Ko, 柯明杰
    Published 2011
    Other Authors: “...Shih-Hsu Huang...”
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  10. 10
    A High-Level Synthesis Approach for Minimum-Area Low-Power Gated Clock Designs
    by Bing-Hung Li, 李秉泓
    Published 2011
    Other Authors: “...Shih-Hsu Huang...”
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  11. 11
    Simultaneous Layer Assignment and Thermal Via Planning for Minimizing The Temperature Rise of Three-Dimensional Integrated Circuits
    by Chen-Yu Huang, 黃震宇
    Published 2014
    Other Authors: “...Shih-Hsu Huang...”
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  12. 12
    TSV-Aware Wrapper Chain Optimization for Three-Dimensional SoCs
    by Yu-Yi Wu, 吳宇益
    Published 2018
    Other Authors: “...Shih-Hsu Huang...”
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  13. 13
    3D IC Test Scheduling under Power and Test Pads Constraints
    by Ming-Hsuan Hsu, 許銘軒
    Published 2016
    Other Authors: “...Shih-Hsu Huang...”
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  14. 14
    Design of Low Power Non-Zero Clock Skew Circuits
    by Da-Chen Tzeng, 曾大誠
    Published 2007
    Other Authors: “...Shih-Hsu Huang...”
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  15. 15
    An FSM Decomposition Structure for Peak Power Minimization
    by Jia-Zong Lin, 林佳宗
    Published 2007
    Other Authors: “...Shih-Hsu Huang...”
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  16. 16
    Zero Skew Gated Clock Tree Design
    by Yuan-Kai Ho, 何元凱
    Published 2008
    Other Authors: “...Shih-Hsu Huang...”
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  17. 17
    Surge Current Minimization of Power Gated Circuits in High Level Synthesis
    by Jheng-Fu Yeh, 葉烝輔
    Published 2009
    Other Authors: “...Shih-Hsu Huang...”
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  18. 18
    A Formal State Encoding Approach for Peak Current Minimization
    by Wei-Chun Peng, 彭偉君
    Published 2009
    Other Authors: “...Shih-Hsu Huang...”
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  19. 19
    Three-Dimensional Power Distribution Network Design at Post-Floorplan Stage
    by Yalamandala Raghu, 羅亞曼
    Published 2009
    Other Authors: “...Shih-Hsu Huang...”
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  20. 20
    Low Power Clock Gating in High Level Synthesis
    Other Authors: “...Shih-Hsu Huang...”
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