POWER AND AREA EFFICIENT 10T SRAM WITH IMPROVED READ STABILITY
In this paper, a 10T Static Random Access Memory bit cell is proposed to meet design specification for performance, stability, area and power consumption. In every state of SRAM cell designs low power and increased noise margin plays an important role. The conventional 6T SRAM cell is very much...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2017-04-01
|
| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_Vol_3_Iss_1_Paper_1_337_344.pdf |