High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler

This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduc...

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Bibliographic Details
Main Authors: Xiaoran Li, Jian Gao, Zhiming Chen, Xinghua Wang
Format: Article
Language:English
Published: MDPI AG 2020-04-01
Series:Electronics
Subjects:
Online Access:https://www.mdpi.com/2079-9292/9/5/725