Multi-Tap FlexHtree application in high performance CPU design
For high performance CPU design, especially on 16 nm and advanced process nodes, with the increase in the number of signoff corner, increasing the clock common path, improving the clock latency correlation on various RC corners, decreasing local skew of design, those are our common view. The Cadence...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2018-08-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000087678 |