PERFORMANCE AND RELIABILITY ANALYSIS FOR VLSI CIRCUITS USING 45nm TECHNOLOGY
The objective of this research paper is to analyze and estimate the reliability of an inverter circuit and two CMOS gate interconnect circuit , a combination of two inverters connected with an RC model as an interconnect structure using cadence virtuoso tool utilizing at gpdk 45 nm technology. R...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
ICT Academy of Tamil Nadu
2015-07-01
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| Series: | ICTACT Journal on Microelectronics |
| Subjects: | |
| Online Access: | http://ictactjournals.in/paper/IJME_paper_2_pp_57_61.pdf |