Hot-Carrier Degradation in Power LDMOS: Selective LOCOS- Versus STI-Based Architecture

Hot-Carrier Degradation in Power LDMOS: Selective LOCOS- Versus STI-Based Architecture

In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are in...

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Bibliographic Details
Main Authors: Andrea Natale Tallarico, Susanna Reggiani, Riccardo Depetro, Andrea Mario Torti, Giuseppe Croce, Enrico Sangiorgi, Claudio Fiegna
Format: Article
Language:English
Published: IEEE 2018-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Hot-carrier degradation/stress
on-resistance degradation
LOCOS
STI
single-particle process
multiple-particle process
Online Access:https://ieeexplore.ieee.org/document/8255610/

Internet

https://ieeexplore.ieee.org/document/8255610/

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