A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS
Transient voltage peaking under very fast electrostatic discharge (ESD), like charged device model (CDM) pulse, is a serious problem to integrated circuits (ICs). A combined TCAD simulation and very fast transmission line pulse (VFTLP) testing method is proposed to thoroughly investigate the transie...
Main Authors: | , , , , , |
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Format: | Article |
Language: | English |
Published: |
IEEE
2020-01-01
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Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9086598/ |