Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis

Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis

Using FPGA-based acceleration of high-performance computing (HPC) applications to reduce energy and power consumption is becoming an interesting option, thanks to the availability of high-level synthesis (HLS) tools that enable fast design cycles. However, obtaining good performance for memoryintens...

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Bibliographic Details
Main Authors: Liang Ma, Luciano Lavagno, Mihai Teodor Lazarescu, Arslan Arif
Format: Article
Language:English
Published: IEEE 2017-01-01
Series:IEEE Access
Subjects:
Cache
high-level synthesis
acceleration
FPGA
optimization
Online Access:https://ieeexplore.ieee.org/document/8030985/

Internet

https://ieeexplore.ieee.org/document/8030985/

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