3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)

3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)

This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bond...

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Bibliographic Details
Main Authors: Wen-Wei Shen, Yu-Min Lin, Shang-Chun Chen, Hsiang-Hung Chang, Tao-Chih Chang, Wei-Chung Lo, Chien-Chung Lin, Yung-Fa Chou, Ding-Ming Kwai, Ming-Jer Kao, Kuan-Neng Chen
Format: Article
Language:English
Published: IEEE 2018-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Backside-via-last TSV
three-dimensional heterogeneous integration
Online Access:https://ieeexplore.ieee.org/document/8315112/

Internet

https://ieeexplore.ieee.org/document/8315112/

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