Dynamic Data Allocation and Task Scheduling on Multiprocessor Systems With NVM-Based SPM
Low-power and short-latency memory access is critical to the performance of chip multiprocessor (CMP) system devices, especially to bridge the performance gap between memory and CPU. Together with increased demand for low-energy consumption and high-speed memory, scratch-pad memory (SPM) has been wi...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2019-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8579198/ |