Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III–V and Ge Materials

Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III–V and Ge Materials

Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devic...

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Bibliographic Details
Main Authors: Sang-Hyeon Kim, Seong-Kwang Kim, Jae-Phil Shim, Dae-Myeong Geum, Gunwu Ju, Han-Sung Kim, Hee-Jeong Lim, Hyeong-Rak Lim, Jae-Hoon Han, Subin Lee, Ho-Sung Kim, Pavlo Bidenko, Chang-Mo Kang, Dong-Seon Lee, Jin-Dong Song, Won Jun Choi, Hyung-Jun Kim
Format: Article
Language:English
Published: IEEE 2018-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Heterogeneous integration
monolithic 3D
sequential 3D
layer transfer
wafer bonding
epitaxial lift-off
Online Access:https://ieeexplore.ieee.org/document/8283617/

Internet

https://ieeexplore.ieee.org/document/8283617/

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