A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS

A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS

Abstract Here, a 4‐level pulse amplitude modulation direct decision feedback equaliser (DFE) with a novel dynamic current‐mode‐logic comparator (DCMLC) is presented. The DCMLC breaks the trade‐off between settling time and regeneration time in traditional CML comparator design by utilizing dynamic l...

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Bibliographic Details
Main Authors: Dengjie Wang, Zeliang Zhao, Ziqiang Wang, Chun Zhang, Zhihua Wang, Hong Chen
Format: Article
Language:English
Published: Wiley 2021-08-01
Series:Electronics Letters
Online Access:https://doi.org/10.1049/ell2.12224

Internet

https://doi.org/10.1049/ell2.12224

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