Design and Investigation of the Junction-Less TFET with Ge/Si<sub>0.3</sub>Ge<sub>0.7</sub>/Si Heterojunction and Heterogeneous Gate Dielectric

Design and Investigation of the Junction-Less TFET with Ge/Si<sub>0.3</sub>Ge<sub>0.7</sub>/Si Heterojunction and Heterogeneous Gate Dielectric

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si<sub>0.3</sub>Ge<sub>0.7</sub>/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is in...

Full description

Bibliographic Details
Main Authors: Tao Han, Hongxia Liu, Shulong Wang, Shupeng Chen, Wei Li, Xiaoli Yang, Ming Cai, Kun Yang
Format: Article
Language:English
Published: MDPI AG 2019-04-01
Series:Electronics
Subjects:
JLTFET
Charge plasma
On-state current
gate-to-drain capacitance
Online Access:https://www.mdpi.com/2079-9292/8/5/476

Internet

https://www.mdpi.com/2079-9292/8/5/476

Similar Items