Modeling of HCD Kinetics Under Full V<sub>G</sub> – V<sub>D</sub> Space, Different Experimental Conditions and Across Different Device Architectures
A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (V<sub>D</sub>) and gate (V<sub>G</sub>) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9207995/ |