Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph

Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph

Represented by application-specific instruction set processors (ASIPs) and array processors, existing cryptographic processors face challenges in application to mobile terminals with sensitive security requirements. Typically, ASIPs have limited computational efficiency and algorithmic adaptability....

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Bibliographic Details
Main Authors: Yufei Zhu, Zuocheng Xing, Jinhui Xue, Zerun Li, Yifan Hu, Yang Zhang, Yongzhong Li
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Stream processor
symmetric cryptograph
area efficiency
parallelism
reconfigurable
Online Access:https://ieeexplore.ieee.org/document/9350281/

Internet

https://ieeexplore.ieee.org/document/9350281/

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