Power Efficiency and Delay Tradeoff of 100G Energy Efficient Ethernet Protocol
This paper investigates the dual-mode power-saving strategy designed for the 100G Energy Efficient Ethernet. The process of this strategy is a sequence of cycles, where each cycle is an interval elapsed between two consecutive instants when the buffer of the Ethernet interface becomes empty. In each...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9107111/ |