PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits

PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits

In this paper, the PAELib - an occupied area and power dissipation estimation library written in VHDL - and its use cases are presented. Estimates are based on the structural description of a CMOS digital circuit made with gates/components included in the library; they can be achieved with systema...

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Bibliographic Details
Main Authors: KIREI, B. S., CHEREJA, V.-I.-M., HINTEA, S., TOPA, M. D.
Format: Article
Language:English
Published: Stefan cel Mare University of Suceava 2019-02-01
Series:Advances in Electrical and Computer Engineering
Subjects:
logic design
software libraries
power dissipation
logic gates
CMOS integrated circuits
Online Access:http://dx.doi.org/10.4316/AECE.2019.01002

Internet

http://dx.doi.org/10.4316/AECE.2019.01002

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