An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement
We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a fiel...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Limited
2014-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2014/230803 |