Vedic division methodology for high-speed very large scale integration applications

Vedic division methodology for high-speed very large scale integration applications

Transistor level implementation of division methodology using ancient Vedic mathematics is reported in this Letter. The potentiality of the ‘Dhvajanka (on top of the flag)’ formula was adopted from Vedic mathematics to implement such type of divider for practical very large scale integration applica...

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Bibliographic Details
Main Authors: Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat
Format: Article
Language:English
Published: Wiley 2014-02-01
Series:The Journal of Engineering
Subjects:
very high speed integrated circuits
SPICE
CMOS logic circuits
dividing circuits
size 90 nm
digit-recurrence architectures
Newton-Raphson architectures
Goldschmidt architectures
CMOS technology
complementary metal oxide semiconductor technology
spice spectre
stage reduction
divider circuitry
dynamic power consumption
propagation delay
Dhvajanka formula
ancient Vedic mathematics
transistor level implementation
high-speed very large scale integration applications
Vedic division methodology
Online Access:http://digital-library.theiet.org/content/journals/10.1049/joe.2013.0213

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http://digital-library.theiet.org/content/journals/10.1049/joe.2013.0213

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