GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning

GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning

This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection of circuit elements, the action masking scheme is employed. It also reduces the size of the action space leading to the impr...

Full description

Bibliographic Details
Main Authors: Hyoungsik Nam, Young In Kim, Jina Bae, Junhee Lee
Format: Article
Language:English
Published: MDPI AG 2021-04-01
Series:Electronics
Subjects:
automated circuit design
CMOS logic gate
reinforcement learning
action masking
Online Access:https://www.mdpi.com/2079-9292/10/9/1032

Internet

https://www.mdpi.com/2079-9292/10/9/1032

Similar Items