DESIGN OF A LOW LATENCY ASYNCHRONOUS ADDER USING EARLY COMPLETION DETECTION
A new method for designing completion detection for asynchronous adders is introduced. The new completion detection is based on the property of a carrymerge tree for parallel-prefix adders where a generate bit at one level will have the same value as that in the previous level if there is no carry...
| Main Authors: | , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Taylor's University
2014-12-01
|
| Series: | Journal of Engineering Science and Technology |
| Subjects: | |
| Online Access: | http://jestec.taylors.edu.my/Vol%209%20Issue%206%20December%2014/Volume%20(9)%20Issue%20(6)%20755-767.pdf |