Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA

Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA

In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to...

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Bibliographic Details
Main Authors: P. Veda Bhanu, Rahul Govindan, Plava Kattamuri, J. Soumya, Linga Reddy Cenkeramaddi
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Network-on-chip
application mapping
torus topology
fault-tolerance
spare core
communication cost
Online Access:https://ieeexplore.ieee.org/document/9380138/

Internet

https://ieeexplore.ieee.org/document/9380138/

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