Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to...
Main Authors: | P. Veda Bhanu, Rahul Govindan, Plava Kattamuri, J. Soumya, Linga Reddy Cenkeramaddi |
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Format: | Article |
Language: | English |
Published: |
IEEE
2021-01-01
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Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9380138/ |
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