CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and pr...

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Bibliographic Details
Main Author: Eitan N. Shauly
Format: Article
Language:English
Published: MDPI AG 2012-01-01
Series:Journal of Low Power Electronics and Applications
Subjects:
low leakage
low power
layout optimization
transistor scaling
leakage-related-stressors
design-aware leakage reduction
Online Access:http://www.mdpi.com/2079-9268/2/1/1/

Internet

http://www.mdpi.com/2079-9268/2/1/1/

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