Migration in Hardware Transactional Memory on Asymmetric Multiprocessor

Migration in Hardware Transactional Memory on Asymmetric Multiprocessor

In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid pu...

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Bibliographic Details
Main Authors: Zivojin Sustran, Jelica Protic
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Shared memory algorithms
multicore architectures
hardware transactional memory
asymmetric multiprocessor
thread migration
Online Access:https://ieeexplore.ieee.org/document/9422791/

Internet

https://ieeexplore.ieee.org/document/9422791/

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