A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs
Due to high parallelism, field-programmable gate arrays are widely used as accelerators in engineering and scientific fields, which involve a large number of operations of vector and matrix. High-performance accumulation circuits are the key to large-scale matrix operations. By selecting the adder a...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2021-01-01
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| Series: | Algorithms |
| Subjects: | |
| Online Access: | https://www.mdpi.com/1999-4893/14/2/30 |