A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs
Due to high parallelism, field-programmable gate arrays are widely used as accelerators in engineering and scientific fields, which involve a large number of operations of vector and matrix. High-performance accumulation circuits are the key to large-scale matrix operations. By selecting the adder a...
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doaj-3f677b73c9ed43b3a1b5bf50c97eb2ea2021-01-21T00:06:27ZengMDPI AGAlgorithms1999-48932021-01-0114303010.3390/a14020030A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAsLinhuai Tang0Zhihong Huang1Gang Cai2Yong Zheng3Jiamin Chen4Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100094, ChinaAerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100094, ChinaAerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100094, ChinaAerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100094, ChinaAerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100094, ChinaDue to high parallelism, field-programmable gate arrays are widely used as accelerators in engineering and scientific fields, which involve a large number of operations of vector and matrix. High-performance accumulation circuits are the key to large-scale matrix operations. By selecting the adder as the reduction operator, the reduction circuit can implement the accumulation function. However, the pipelined adder will bring challenges to the design of the reduction circuit. To solve this problem, we propose a novel reduction circuit based on binary tree path partition, which can simultaneously handle multiple data sets with arbitrary lengths. It divides the input data into multiple groups and sends them to different iterations for calculation. The elements belonging to the same data set in each group are added to obtain a partial result, and the partial results of the same data set are added to achieve the final result. Compared with other reduction methods, it has the least area-time product.https://www.mdpi.com/1999-4893/14/2/30pipelinevector reductionaccumulatorFPGAs |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
Linhuai Tang Zhihong Huang Gang Cai Yong Zheng Jiamin Chen |
spellingShingle |
Linhuai Tang Zhihong Huang Gang Cai Yong Zheng Jiamin Chen A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs Algorithms pipeline vector reduction accumulator FPGAs |
author_facet |
Linhuai Tang Zhihong Huang Gang Cai Yong Zheng Jiamin Chen |
author_sort |
Linhuai Tang |
title |
A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs |
title_short |
A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs |
title_full |
A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs |
title_fullStr |
A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs |
title_full_unstemmed |
A Novel Reduction Circuit Based on Binary Tree Path Partition on FPGAs |
title_sort |
novel reduction circuit based on binary tree path partition on fpgas |
publisher |
MDPI AG |
series |
Algorithms |
issn |
1999-4893 |
publishDate |
2021-01-01 |
description |
Due to high parallelism, field-programmable gate arrays are widely used as accelerators in engineering and scientific fields, which involve a large number of operations of vector and matrix. High-performance accumulation circuits are the key to large-scale matrix operations. By selecting the adder as the reduction operator, the reduction circuit can implement the accumulation function. However, the pipelined adder will bring challenges to the design of the reduction circuit. To solve this problem, we propose a novel reduction circuit based on binary tree path partition, which can simultaneously handle multiple data sets with arbitrary lengths. It divides the input data into multiple groups and sends them to different iterations for calculation. The elements belonging to the same data set in each group are added to obtain a partial result, and the partial results of the same data set are added to achieve the final result. Compared with other reduction methods, it has the least area-time product. |
topic |
pipeline vector reduction accumulator FPGAs |
url |
https://www.mdpi.com/1999-4893/14/2/30 |
work_keys_str_mv |
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