Design, implementation and performance comparison of multiplier topologies in power-delay space
With the advancements in the semiconductor industry, designing a high performance processor is a prime concern. Multiplier is one of the most crucial parts in almost every digital signal processing applications. This paper addresses the implementation of an 8-bit multiplier design employing CMOS ful...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2016-03-01
|
| Series: | Engineering Science and Technology, an International Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098615001287 |