Junctionless Poly-Si Nanowire FET With Gated Raised S/D
The short-channel effect (SCE) is an important issue in CMOS technology. In this paper, a junctionless (JL) poly-Si nanowire FET (NW-FET) with gated raised source/drain (S/D) was demonstrated to suppress the SCE. The gated raised S/D structure enhances the control of the channel by the gate. Therefo...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2016-01-01
|
| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/7370877/ |