Parity Codes Used for On-Line Testing in FPGA
This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appeara...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
CTU Central Library
2005-01-01
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| Series: | Acta Polytechnica |
| Subjects: | |
| Online Access: | https://ojs.cvut.cz/ojs/index.php/ap/article/view/788 |