A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

Abstract This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI...

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Bibliographic Details
Main Authors: Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, Chrong Jung Lin, Ya-Chin King
Format: Article
Language:English
Published: SpringerOpen 2017-06-01
Series:Nanoscale Research Letters
Subjects:
CMOS logic process
Static random access memory
Resistive random access memory
Logic non-volatile memory
Online Access:http://link.springer.com/article/10.1186/s11671-017-2191-9

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http://link.springer.com/article/10.1186/s11671-017-2191-9

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