Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ra...

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Bibliographic Details
Main Authors: Qingzhu Zhang, Jie Gu, Renren Xu, Lei Cao, Junjie Li, Zhenhua Wu, Guilei Wang, Jiaxin Yao, Zhaohao Zhang, Jinjuan Xiang, Xiaobin He, Zhenzhen Kong, Hong Yang, Jiajia Tian, Gaobo Xu, Shujuan Mao, Henry H. Radamson, Huaxiang Yin, Jun Luo
Format: Article
Language:English
Published: MDPI AG 2021-03-01
Series:Nanomaterials
Subjects:
nanosheet (NS)
gate-all-around (GAA)
channel release
parasitic channel
suppression
Online Access:https://www.mdpi.com/2079-4991/11/3/646

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https://www.mdpi.com/2079-4991/11/3/646

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