A low-cost concurrent TSV test architecture with lossless test output compression scheme.
As the traditional IC design migrates to three-dimensional integrated circuits (3D-ICs) design, new challenges need to be considered carefully to solve its reliability and yield issues. 3D-ICs using through-silicon-vias (TSVs) can have latent defects such as resistive open and bridge defects, which...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Public Library of Science (PLoS)
2019-01-01
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| Series: | PLoS ONE |
| Online Access: | https://doi.org/10.1371/journal.pone.0221043 |