An FPGA-Based LDPC Decoder With Ultra-Long Codes for Continuous-Variable Quantum Key Distribution

An FPGA-Based LDPC Decoder With Ultra-Long Codes for Continuous-Variable Quantum Key Distribution

In this paper, we propose a good decoding performance, low-complexity, and high-speed decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum-product decoding scheme. To reduce implementation complexity and hardware resource consumption, the messages in the iteration pro...

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Bibliographic Details
Main Authors: Shen-Shen Yang, Jian-Qiang Liu, Zhen-Guo Lu, Zeng-Liang Bai, Xu-Yang Wang, Yong-Min Li
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Low-density parity check (LDPC) decoder
field programmable gate array (FPGA)
ultra-long codes
layered sum-product decoding
side information
Online Access:https://ieeexplore.ieee.org/document/9376906/

Internet

https://ieeexplore.ieee.org/document/9376906/

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