Mechanisms for functional testing of hardware models at different levels of abstraction
It is known that at different design stages different representations of a target system are used (a general description of the system's architecture is step by step concretized up to a physical layout). Depending on the project maturity engineers apply different verification methods and, in pa...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Ivannikov Institute for System Programming of the Russian Academy of Sciences
2018-10-01
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| Series: | Труды Института системного программирования РАН |
| Subjects: | |
| Online Access: | https://ispranproceedings.elpub.ru/jour/article/view/1057 |