Analysis of Minimal LDPC Decoder System on a Chip Implementation
This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The p...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Spolecnost pro radioelektronicke inzenyrstvi
2015-09-01
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| Series: | Radioengineering |
| Subjects: | |
| Online Access: | http://www.radioeng.cz/fulltexts/2015/15_03_0783_0790.pdf |