OPTIMIZATION OF CODE IDENTIFIER USING TGL AND DVL
The design of 2:4 and 4:16 decoder using 14 multiple logics is proposed. As the power is very important key role in IC. Also to provide lower power consumption with high performance is challenging task. To provide such a performance the design oflow power high performance is discussed. The decoder i...
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| Format: | Article |
| Language: | English |
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Yeshwantrao Chavan College of Engineering, India
2021-05-01
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| Series: | Journal of Research in Engineering and Applied Sciences |
| Subjects: | |
| Online Access: | http://www.mgijournal.com/Data/Issues_AdminPdf/251/OPTIMIZATION%20OF%20CODE%20IDENTIFIER%20USING.pdf |